The pursuit of making computing systems more powerful and more power efficient has led to advancement in interface communications to improve throughput without increasing, and ideally reducing, energy consumption. Often, as clock speeds increase, a desire to increase data transition times on interface busses to match the faster clock speeds exists. Some systems have implemented multi-level (e.g., more than two levels) bus architectures to increase throughput over an interface bus. However, an inherent characteristic of multi-level signals is that time shifts (e.g., jitter) may occur between consecutive symbols. That is, the timing between symbol transitions of the output signals determined from the signal line values may vary within a symbol period due to differences in transition magnitudes. For example, an output signal having a constant slew rate will take longer to transition between the max levels (e.g., VH to VL) than between a mid-level and a max level (e.g., VH/2 to VH). The inherent jitter may reduce the available setup and hold times between symbols, sometimes by as much as 20%. As clock speeds increase, the reduction of set-up and hold times can lead to reduced robustness and reliability in reading data on an interface using this type of system.